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CE-1900 Homework

Homework must be submitted on paper and will normally be turned in in class or in lab. Homework may also be left in my mailbox in L350. Either handwritten work or a computer printout is acceptable. Remember the general course policies; you may discuss and work on problems with other students, but you must develop your own solution to each problem.

Abbreviation of dates: WmDn refers to the nth day of lecture in the mth week of class. WmL refers to the lab in week m. For example, W3D2 is the 2nd lecture of week 3 (regardless of whether the lab period is before or after the 2nd lecture period).

W1D1 (10 points, due beginning of W1L)

  1. (2 points) List the powers of 2 starting with the 0th power and ending with the 16th power.
  2. (3 points) P2.1-a, c, and f. (Page 50, decimal to binary.) Show all calculations.
  3. (3 points) P2.2-b, c, and f. (Unsinged binary to ...) To decimal only. (Will do hexadecimal and octal for day 2 homework.) Illustrate key steps..
  4. (2 points) In decimal (base 10), we can quickly multiply by 10 by concatenating a 0 to the right of a number. What is the result of concatenating a 0 to the right of a binary number? Demonstrate this for 1012, which becomes 10102.

W1D2 (10 points, due W2D1)

  1. (3 points) P2.2-b, c, and f. Complete problem 3 from day 1 (hexadecimal and octal). Illustrate key steps. Hint: It is easier to work from base 2 than from base 10.
  2. (1 point) Convert 25178 to binary.
  3. (3 points) P2.3-b and e. Illustrate key steps..
  4. (3 points) Add the following pairs of 8-bit binary numbers, under the constraint that there are 8 bits available for the result. Interpret the results and indicate whether an unsigned overflow occurred. Explain the problem that an unsigned overflow indicates.
    1. 1010 0101 + 0110 1001
    2. 0011 1111 + 0001 1000

W2D1 (10 points, due W2D2)

  1. (3 points) Draw a truth table for the 3-input AND and OR functions.
  2. (3 points) P2.4-b and g
  3. (4 points) P2.6-b, c, and f

W2D2 (10 points, due W3D1)

  1. (4 points) P2.5-d
  2. (6 points) P2.11-a

W3D1 (10 points, due W3D2)

  1. F = a'bc' + a'bc + ab'c' + ab'c + abc
    1. (1 point) Draw the truth table for F. (Note: For equations in canonical form, beginning this week, it is not necessary to show intermediate steps in the truth table.)
    2. (1 point) Express F as a sum of minterms using mi notation
    3. (1 point) Express F as a sum of minterms using Σ notation
    4. (3 points) Draw a Karnaugh map for F. Box in the prime implicants (for each 1-minterm, the largest subcube [see class notes or textbook] that contains it; some of these will cover more than 1 term, so you will generally have far fewer boxes than minterms). Label each prime implicant with the value(s) of the 1-3 variables that are needed to define it.
    5. (2 points) Using your result from the previous step, write a minimized sum-of-products version of F.
    6. (2 points) Show how to implement your equation from the previous step using NOT/AND/OR gates. (Or, if you prefer, only NAND gates; see section 3.3.)

W4D1 (20 points, due W4D2)

  1. (13 points) See problem 3.27(c) on page 96 of your textbook.
    1. (3 points) Complete the problem, taking the best possible advantage of don't cares. Be sure that you label, on the K-map, each term that you select for the reduced function. Also, state the fully reduced SOP function.
    2. (2 points) Re-do all parts of the previous item, including labeled K-map reduction, but this time ignore the don't cares (they must output 0).
    3. (1 point) Calculate the number of gates (NOT, 2-input AND, and 2-input OR only) required to implement your equation from (a).
    4. (1 point) Calculate the number of gates (NOT, 2-input AND, and 2-input OR only) required to implement your equation from (b).
    5. (1 point) Calculate the reduction ratio between the two implementations above.
    6. (2 points) Implement the equation from (a) using the gates that you tallied in (c).
    7. (3 points) Convert the circuit from (f) so that it uses only NAND gates.
  2. (7 points) See problem 3.1(d) on page 92 of your textbook.
    1. (3 points) Draw the truth table, labeling and evaluating as many intermediate terms as you need, but at least the outputs of all the multi-input gates.
    2. (2 points) Draw the K-map for the truth table you just derived. Use it to derive the most reduced SOP version of the function, showing work as in the previous problem.
    3. (1 point) Implement your fully reduced equation. This time, in addition to the NOT and 2-input AND and OR gates, 3-input AND and OR gates are available. Use the minimum number of gates.
    4. (1 point) Calculate the reduction ratio for your circuit drawn in the previous step compared with the original circuit given in the textbook.

W5D2 (7 points, due W6D1)

  1. (1 point) Calculate the range of an 8-bit unsigned number.
  2. (1 point) Calculate the range of an 8-bit signed number.
  3. (2 points) Convert -100 and -20 to 8-bit signed format.
  4. (1 point) Perform binary addition of the 2 8-bit numbers above.
  5. (1 point) Interpret the sum as the unsigned result of adding two unsigned numbers. Is there unsigned overflow?
  6. (1 point) Interpret the sum as the signed result of adding two signed numbers. Is there signed overflow?

W7D2 (10 points, due W8L)

  1. Design an ALU that performs the following 4 operations:

    (3 points) Similar to the example on page 116, the design will consist of

    1. (required) a function table
    2. (optional) a truth table for the logic extender
    3. (optional) a truth table for the arithmetic extender
    4. (optional) a truth table for the carry extender

    (4 points) Next, reduce the LE, AE, and CE equations. Some of the equations may be simple enough to write directly from the tables above. For the remaining ones, however, it will be necessary to show a K-map to ensure that you have found the simplest sum-of-products implementation. (An alternative design method is to use 4-1 MUXes, but for this problem you must use K-maps.)

    (3 points) The final element of the design is to show how these 3 components, which you may now represent using block symbols (do not draw all the gates), are connected to FAs (full adders) to create an ALU. Be sure to show at least a 2-bit ALU so that the connections of the FA carry inputs and outputs are unambiguous.

W8D1 (10 points, due W8D2)

  1. P4.14
  2. P4.16

W8D2 (10 points, due W9D1)

  1. (5 points) P4.18
  2. (5 points) P4.25

W9D1 (10 points, due W9D2)

  1. P4.19. Do this in Quartus, turning in your schematic for the 4:2 priority encoder and your VHDL or schematic for the 2:1 priority encoder. If you choose to use busses for the inputs to the 2:1 priority encoder, they must be named with care. For example, you may have a need to take 2 signals off a bus of 4 signals and put them onto another bus. One way to do this is...

    X[3..0] =============== 
           |       |
           |X[3]   |X[2]
           |       |
          ====================
                       X[3..2]

    To keep the wiring simpler, you may wish to avoid using busses for this assignment.

    You may use the "21mux" component that is available in Quartus, or you may implement your own 2:1 MUX.

W10D2 (10 points extra credit [optional], due W10 Friday)

  1. (4 points) P4.27
  2. (3 points) P4.30
  3. (3 points) P4.33: Hint: You only need 23 input rows. Write outputs as needed in terms of the di inputs.

This page was last updated on Monday, 09-Nov-2009 16:23:29 CST.