Static Hazards

Introduction

Logic hazards occur when the output deviates from it's intended logic level for a brief period of time. They arise when the differences in the timing delays for different portions of the circuit cause the inputs to the final gate in the circuit to be an unexpected combination.

In the following example we will see that the inputs to the final OR gate will go to 00 when passing from the desired input of 10 to the desired input of 01. One should note that both of the desired combinations produce a 1 at the output of the OR gate whereas the unexpected input of 00 produces an unexpected output of 0 for a brief period of time.

Hazard Basics

The hazard is called a static hazard if it occurs when the output should remain constant when only one input variable is changed.
A static 1 hazard occurs when the output should remain 1, but drops to 0.
A static 0 hazard occurs when the output should remain 0, but drops to 1.

Sum of Products Implementations

Static 1 hazards occur in SOP implementations.
Static 0 hazards do not occur in SOP implementations.
The previous two statements apply to NAND/NAND implementations as well as SOP implementations.

At first glance, these statements seem very broad and almost foolish. Can I really say that I will never see a Static 0 hazard in a Sum of Products circuit?

By looking at the example, F = A'B' + BC, we may be able to determine if I really am a fool. It is clear that this is a sum of the Products A'B' and BC.

Let's take a closer look at this expression. F is 1 when either A'B' is 1 or BC is 1 (or both are 1). If our input is 000, then A'B' = (0)'(0)' = (1)(1) = 1 so the output of A'B' is 1. If we change the input to 001, A'B' should remain at 1 since neither A nor B change. (This change corresponds to the time interval 0-80ns in the figure below.) So what's the big deal? The big deal is that at least one of the product terms in F stays at 1. In this case there is no opportunity for F to go to 0 because A'B' remains a 1 the entire time and, of course, 1 + ANYTHING = 1. The same reasoning applies for changing between input 011 and 111 since the inputs B and C don't change, so the product term BC remains 1 the entire time. A glance at the K-map will reveal that the input combinations 000 and 001 correspond moving between the ones in the grouping for A'B', and the inputs 011 and 111 correspond to moving between the ones in the grouping for BC. It is evident that changing the input while remaining within a grouping on the K-map will not produce a static 1 hazard since the OR gate will always see a 1 at one of it's inputs. Note that this same reasoning can be applied to more complicated circuits with more than just a two product terms.

We cannot have a static 1 hazard when we go from an input combination that produces a 1 to an input combination that produces a 0 or vice versa because such hazards are called dynamic hazards.

Therefore, the only place that we have not ruled out the potential for static 1 hazards to occur is when we change input combinations that occur between two different groupings of ones. For our circuit, we switch between groups of ones when we go from input 001 to 011 (160-240ns) or back (200-240ns). When we go from input 001 to 011 we are moving out of the grouping that gave us the A'B' product term and going into the grouping that gave us the BC term. In other words, A'B' is changing from a 1 to a 0 and BC is changing from a 0 to 1. We can see from the timing diagram that we encounter a static 1 hazard only when we go from 011 to 001.

Here we are moving from the BC grouping to the A'B' grouping. The hazard occurs because BC changes from 1 to 0 before A'B' changes from 0 to 1. In fact, both A'B' and BC are 0 for ten nanoseconds (210-220ns). (A'B' takes longer to change because the changes to the input must trickle through the inverters before they arrive at the input of the AND gate.) Now, when both A'B' and BC are input into the OR gate, the OR gate produces a 0 (our static 1 hazard).

Those of you who are paying attention may have noticed that we encounted a static hazard when moving from 011 to 001 but not when moving from 001 to 011. At this point, it may be worth asking ourselves why that is the case. Why is that the case? Again, it boils down to what the OR gate "sees" for input. When going from 011 to 001 the A'B' term changes from 0 to 1 more slowly than the BC term changes from 1 to 0. This results in a brief period of time where the OR gate has inputs of 00. On the other hand, when going from 001 to 011 the A'B' term changes from 1 to 0 more slowly than the BC term changes from 0 to 1. This results in a brief period of time where the OR gate has inputs of 11. Here the output of the OR gate remains at a 1, and no hazard occurs.

Up until now we have dealt with static 1 hazards only. We still haven't attempted to justify the seemingly most reckless statement. Here it is again for your convenience:

Static 0 hazards do not occur in SOP implementations.

We will not see any static 0 hazards because both of the product terms (A'B' and BC) must be 0 whenever F is 0. Whenever we change from one input that produces a 0 to another input that produces a 0, both A'B' and BC remain at 0 the entire time. Therefore, the inputs to the OR gate will remain 0 when changing between inputs that result in a 0 for F. These few sentences may not be enough to convince you of the truth. If not, I would suggest that you build the circuit and play around with it. See if you can get a static 0 hazard. If you can, please let me know!

We now attempt to justify the third proposition:

The previous two statements apply to NAND/NAND implementations as well as SOP implementations.

We have two options here. We could go through all of the logic cases in a similar fashion to the above, or we could wave our hands wildly and hope that we will be believed. I have chosen to lead us in a hand waving session rather than labor through all of the details above. The basic argument is this: NAND/NAND implementations are identical to AND/OR implementations. This can be seen by applying DeMorgan's Law to either the NAND/NAND expression to get an AND/OR expression or to the AND/OR expression to get a NAND/NAND expression. For our example we have F = A'B' + BC = [(A'B')'(BC)']' = [(A' nand B') nand (B nand C)].

It should be clear from the above discussion that we can eliminate the static 1 hazard in the previous circuit by adding an extra product term. The new circuit should be F = A'B' + BC + A'C with the corresponding K-map:

Can you explain why this eliminates our static 1 hazard?

Product of Sums Implementations

Static 0 hazards occur in POS implementations.
Static 1 hazards do not occur in POS implementations.
The previous two statements apply to NOR/NOR implementations as well as POS implementations.

The reasoning here is similar to that of the SOP circuit except now our final gate is an AND gate. With the SOP circuit we encountered problems when the product terms switched between 0 and 1. Essentially, the the static 1 hazard appeared when the inputs to the final (OR) gate changed. As one might expect, this is where we will encounter static 0 hazards. The only difference is that our final gate is an AND gate instead of an OR gate.

In the case of an OR gate we ran into problems when we changed from 01 to 10 (or vice versa) and momentarily went to 00. This was a problem because 00 produces a different output (0) than 01 or 10 do (1). Now, in the case of an AND gate 01, 10, and 00 all result in the same output (0). Therefore, we don't need to fret if this occurs. Our problem here is when we switch the inputs to the AND gate from 01 to 10 (or vice versa) and momentarily pass through 11. This gives us a static 0 hazard because our output should remain at 0 (the result of 01 or 10 as inputs to an AND gate) but goes to 1 when 11 is presented to the AND gate for a brief period of time.

Some day I may get around to writing up a description for F = (A' + B')(B + C) similar to the one done for F = A'B' + BC. Until then your life (and mine) will be incomplete. Please try to adjust to it.

A revised Acrobat (pdf) version is available.